The invention relates to a semiconductor device comprising a matrix of storage cells which are arranged in rows and columns, each storage cell comprising a non-volatile storage transistor and an access transistor connected in series therewith, the storage transistor having an insulated control electrode and the access transistor having an insulated gate electrode, and the gate electrodes of the access transistors of a row of storage cells being connected to an access line common to this row and the access lines being connected to a decoder for driving the access lines with selection signals, whereby the access transistors of a selected row of storage cells are conducting, the access transistors of the remaining rows of storage cells are non-conducting, and each row of storage cells comprises at least two groups of storage cells. In each of these groups the insulated control electrodes are connected to each other and by means of a switch controllable by a common access line to a control line common to a column of groups, and each storage cell at one end of the series arrangement is connected to a first conductor common to column of storage cells and at the other end of the series arrangement being coupled to a second conductor common to at least a column of storage cells.
Such a semiconductor device is known from U.S. Pat. No. 4,266,283. This Patent relates to an electrically alterable read-only memory (EAROM or EEROM), in which the storage transistors are of the type having a floating gate electrode. Via the control lines groups of storage cells or bytes can be selected. The control lines are each connected through a selection switch to a common line to which a control signal is applied. It is determined by means of this control signal whether information can be written, read or erased in the memory.